U.S. Pat. No. 5,864,156 discloses lining the upper region of the sidewalls of contact holes with a spacer material.
U.S. Pat. No. 5,792,687 discloses a method for forming contact holes, spacers being formed on the sidewalls of contact holes on an interlevel dielectric.
IBM Technical Disclosure Bulletin, Vol. 34, No. 4B, Sep. 1, 1991, pages 277 to 279, discloses the fabrication of contact plugs which are placed beside one another with the interposition of a spacer.
Although applicable to arbitrary integrated circuits, in principle, the present invention and the problem area on which it is based are explained with regard to integrated DRAM circuits using silicon technology.
The general problem area on which the present invention is based is that, during the fabrication of a common self-aligned bit line contact of a DRAM memory cell pair, the widening of the contact hole or its lateral offset leads to a risk of short circuits with respect to adjacent bit lines, which risk grows as design rules become smaller. What is increasingly problematic is the rising aspect ratio of the bit line contact owing to the decreasing horizontal and increasing vertical dimensions, i.e. the height of the gate stack.
FIG. 3 shows a diagrammatic illustration of a known integrated DRAM circuit using silicon technology.
In FIG. 3, 1 designates a silicon semiconductor substrate in which an active region or circuit region SS is provided in a manner surrounded by isolation trenches STI.
An insulation layer IS, for example made of BPSG or SiO2, is situated above the circuit region SS and the isolation trenches STI. A contact hole KL is introduced into the insulation layer IS, said contact hole containing a contact which has a polysilicon contact plug PP in the lower region and a bit line BL2 in the upper region. Situated adjacent to the bit line BL2 are further bit lines BL1 and BL3 in corresponding bit line trenches BG1 and BG3, respectively.
What is problematic in the case of this arrangement is the fact that the contact hole KL may have a certain offset with respect to the circuit region SS and with respect to the adjacent bit lines, a displacement toward the left-hand side of FIG. 3 in the present example. The bit lines BL1, BL2, BL3 are fabricated in such a way that a metal layer made of tungsten is deposited above the bit line trenches and above the substrate surface, which metal layer is polished back in a subsequent process step by means of a chemical mechanical polishing process. By virtue of the offset of the contact hole KL toward the left, a short circuit between the bit lines BL1 and BL2 can occur at the location designated by BBS, which disturbs the function of said bit lines.
In this case, the bit line contact hole plane, which is relatively non critical lithographically in terms of the design, is fabricated with minimal contact hole dimensions in order to alleviate the problem of short-circuiting with respect to the adjacent bit line fabricated in a separate lithography. The overlay requirements are very high in this case. This complicates the lithography and the contact hole etching and makes them more expensive without fundamentally solving the problem. Moreover, there is an increase in the risk of inadequately opened bit line contacts at the contact base. The requirements made of the alignment of the bit line contact with respect to the active region or circuit region SS are increased. This results in a general contradiction which becomes more and more problematic with further shrinks.